A Radiation-Hard Dual Channel 4-bit Pipeline for a 12-bit 40 MS/s ADC Prototype with extended Dynamic Range for the ATLAS Liquid Argon Calorimeter Readout Electronics Upgrade at the CERN LHC

The design of a radiation-hard dual channel 12-bit 40 MS/s pipeline ADC with extended dynamic range is presented, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four Multiplying Digital-to-Analog Converters with nominal 12-bit resolution each. The design, fabricated in the IBM 130 nm CMOS process, shows a performance of 68 dB SNDR at 18 MHz for a single channel at 40 MS/s while consuming 55 mW/channel from a 2.5 V supply, and exhibits no performance degradation after irradiation. Various gain selection algorithms to achieve the extended dynamic range are implemented and tested.Comment: 22 pages, 22 figures, accepted by JINS

A radiation-hard dual-channel 12-bit 40 MS/s ADC prototype for the ATLAS liquid argon calorimeter readout electronics upgrade at the CERN LHC

The readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider requires a radiation-hard ADC. The design of a radiation-hard dual-channel 12-bit 40 MS/s pipeline ADC for this use is presented. The design consists of two pipeline A/D channels each with four Multiplying Digital-to-Analog Converters followed by 8-bit Successive-Approximation-Register analog-to-digital converters. The custom design, fabricated in a commercial 130 nm CMOS process, shows a performance of 67.9 dB SNDR at 10 MHz for a single channel at 40 MS/s, with a latency of 87.5 ns (to first bit read out), while its total power consumption is 50 mW/channel. The chip uses two power supply voltages: 1.2 and 2.5 V. The sensitivity to single event effects during irradiation is measured and determined to meet the system requirements

Design Techniques for Analog-to-Digital Converters in Scaled CMOS Technologies

Analog-to-digital converters (ADCs) are analog pre-processing systems that convert the real life analog signals, the input of sensors or antenna, to digital bits that are processed by the system digital back-end. Due to the various issues associated with CMOS technology scaling such as reduced signal swings and lower transistor gains, the design of ADCs has seen a number of challenges in medium to high resolution and wideband digitization applications. The various chapters of this thesis focus on efficient design techniques for ADCs that aim to address the challenges associated with design in scaled CMOS technologies. This thesis discusses the design of three analog and mixed-signal prototypes: the first prototype introduces current pre-charging (CRP) techniques to generate the reference in Multiplying Digital-to-Analog Converters (MDACs) of pipeline ADCs. CRP techniques are specifically applied to Zero-Crossing Based (ZCB) Pipeline-SAR ADCs in this work. The proposed reference pre-charge technique relaxes power and area requirements for reference voltage generation and distribution in ZCB Pipeline ADCs, by eliminating power hungry low impedance reference voltage buffers. The next prototype describes the design of a radiation-hard dual-channel 12-bit 40MS/s pipeline ADC with extended dynamic range, for use in the readout electronics upgrade for the ATLAS Liquid Argon Calorimeters at the CERN Large Hadron Collider. The design consists of two pipeline A/D channels with four MDACs with nominal 12-bit resolution each, that are verified to be radiation-hard beyond the required specifications. The final prototype proposes Switched-Mode Signal Processing, a new design paradigm that achieves rail-to-rail signal swings with high linearity at ultra-low supply voltages. Switched-Mode Signal Processing represents analog information in terms of pulse widths and replaces the output stage of OTAs with power-efficient rail-to-rail Class-D stages, thus producing Switched-Mode Operational Amplifiers (SMOAs). The SMOAs are used to implement a Programmable Gain Amplifier (PGA) that has a programmable gain from 0-12dB